1. Field of the Invention
The present invention relates to a semiconductor device which is suitable to a field shield isolation structure and has such a structure that electrodes opposed to a semiconductor layer are insulated from each other by an insulating layer, and a method of fabricating the same, and more particularly, it relates to an improvement for preventing or relieving deterioration of characteristics and reliability of the device resulting from the insulating layer.
2. Description of the Background Art
FIG. 49 is a sectional perspective view showing the sectional structure of a conventional semiconductor device having a field shield isolation structure, which forms the background of the present invention. This semiconductor device is structured as that having a semiconductor to be provided with transistor elements or the like which is formed as a film on an insulating substrate, i.e., an SOI (semiconductor-on-isolation) semiconductor device.
As shown in FIG. 49, a buried oxide film 2 is formed on a support substrate 1, and a semiconductor layer is formed on this buried oxide film 2 as an SOI layer 3 in this semiconductor device 151. This SOI layer 3 includes a number of areas (NMOS areas) of NMOS transistor elements and a number of areas (PMOS areas) of PMOS transistor elements. In order to electrically isolate the plurality of element areas from each other, flat plate type FS electrodes (field shielding electrodes) 5 are formed to be opposed to isolation areas which are set between the respective element areas in the SOI layer 3.
Each element area of the SOI layer 3 is connected with drain and source electrodes, i.e., main electrodes, through a contact hole 7 which is provided in an insulating layer (not shown), and with a body contact electrode through another contact hole 9. A gate electrode 6 is opposed to each element area, while a gate wire is connected with this gate electrode 6 through still another contact hole 8.
Each FS electrode 5 is covered with an FS insulating layer (field shielding insulating layer) 4 which is made of an oxide. The FS insulating layer 4 electrically insulates the FS electrode 5 and the gate electrode 6 from each other.
In this device 151, a reverse bias voltage is applied to each FS electrode 5 for cutting off the SOI layer 3 of the isolation area, thereby implementing electrical isolation between the element areas. As another structure for implementing such isolation between element areas, a LOCOS structure of implementing isolation by selectively oxidizing the SOI layer 3, or a mesa isolation structure of selectively etching the SOI layer 3 thereby isolating the element areas from each other is widely known.
In the LOCOS structure or the mesa isolation structure, however, stress concentrates to a local portion the SOI layer 3, due to local oxidation or local etching of the SOI layer 3. This results in a problem in reliability of the device such as generation of a leakage current. In the device 151, on the other hand, neither local oxidation nor etching is necessary due to the employment of the field shield isolation structure, whereby stress concentration can be avoided and relatively high reliability can be advantageously attained while suppressing a leakage current.
In the conventional field shield isolation structure, however, various problems in reliability resulting from the structure and the method of fabricating the same are still unsolved. FIG. 50 is a front sectional view showing a part of a rectangular frame A appearing in FIG. 49 in an enlarged manner, for clearly illustrating these problems. Circular frames B, C and D shown in FIG. 50 illustrate parts related to these problems.
As shown in FIG. 50, the FS insulating layer 4 has an upper insulating layer 12 covering an upper part of the FS electrode 5, and a side wall (side wall part) 13 covering each edge portion 16 of the FS electrode 5. On the other hand, a lower insulating layer 11 is interposed between a major surface of the SOI layer 3 and the flat plate type FS electrode 5 opposed thereto, for electrically insulating the same from each other. Gate insulating films 14 are further formed on the major surface of the SOI layer 3. The gate insulating films 14 are made of an oxide, similarly to the FS insulating layer 4.
The gate electrode 6 is formed to be along surfaces of one gate insulating film 14, the side wall 13 and the upper insulating layer 12. Namely, the gate electrode 6 holds the gate insulating film 14, to be opposed to the major surface of the SOI layer 3 while maintaining electric insulation. The upper insulating layer 12 and the side wall 13 maintain electric insulation between the FS electrode 5 and the gate electrode 6.
FIGS. 51 to 55 are step diagrams showing fabrication steps causing a first problem shown by the circular frame B in FIG. 50. In a conventional method of fabricating the device 151, a composite obtained by successively forming the buried oxide film 2 and the SOI layer 3 on one major surface of the support substrate 1 is first prepared, as shown in FIG. 51. Then, an oxide film 21, a polysilicon layer 22 doped with an impurity, and an oxide layer 23 are formed in this order on a surface of the SOI layer 3 of this composite. Thereafter a patterned resist layer 24 is formed on the oxide layer 23.
Then, dry etching is performed through the resist layer 24 serving as a screen (mask), thereby selectively removing the oxide layer 23 and forming the upper insulating layer 12, as shown in FIG. 52. If wet etching is performed in place of the dry etching, side wall surfaces of the upper insulating layer 12 are retreated toward the interior of the resist layer 24 in the form of concave curved surfaces, as shown by numeral 26 in FIG. 52. This brings unpreferable results in the performance of the insulation and isolation between the FS electrode 5 and the gate electrode 6. Therefore, the dry etching is selected as the method of forming the upper insulating layer 12.
In this step, deposition films 25 are formed on surfaces of side portions of the upper insulating layer 12 as byproducts. The deposition films 25 are formed by adsorption of an etchant such as CF.sub.4, for example, employed for the dry etching. A major surface of the oxide layer 23 is continually etched by accelerated CF.sub.4 or the like in the process of the dry etching, whereby no such byproduct remains on the surface of the polysilicon layer 22. On hardly etched side walls of the upper insulating layer 12, however, the etchant remains as the deposition films 25.
Then, dry etching is further performed through the resist layer 24 serving as a screen, thereby selectively removing the polysilicon layer 22 and the oxide film 21, as shown in FIG. 53. At this time, the etching is performed while maintaining the deposition films 25 unremoved along with the resist layer 24. Consequently, the FS electrode 5 is formed from the polysilicon layer 22, while the lower insulating layer 11 is formed from the oxide film 21.
Thereafter the resist layer 24 and the deposition films 25 are removed, as shown in FIG. 54. Then, the side walls 13 are prepared from the same material as the lower and upper insulating layers 11 and 12, to cover the side wall surfaces of the upper insulating layer 12 and edge portions 16 of the FS electrode 5, as shown in FIG. 55. Thereafter the gate insulating films 14 are formed on the major surface of the SOI layer 3, and the gate electrode 6 is formed on one gate insulating film 14 and the FS insulating layer 4, as shown in FIG. 50.
The device 151 is fabricated through the aforementioned steps, and hence the edge portions 16 of the FS electrode 5 project outward beyond the side wall surfaces of the upper insulating layer 12, as shown in FIG. 55. In other words, top portions 15 of the side walls 13 are inwardly retreated from the edge portions 16 of the FS electrode 5. As shown in a circular frame F in FIG. 55, therefore, the thickness of each side wall 13 covering each edge portion 16 cannot be sufficiently ensured.
This means that the distance between one edge portion 16 and the gate electrode 6 is not sufficiently ensured, as shown in the circular frame B in FIG. 50. Consequently, the electrostatic capacitance between the FS electrode 5 and the gate electrode 6 is unnecessarily increased, to hinder a high-speed operation of the device. This also brings such a problem that a short readily takes place across the FS electrode 5 and the gate electrode 6.
While treatment employing HF (hydrofluoric acid) is performed before forming the gate insulating films 14 in order to clean the surface of the SOI layer 3 and to remove a natural oxide film, the thickness of each side wall 13 is further reduced by this HF treatment. Consequently, the margin with respect to the distance between the FS electrode 5 and the gate electrode 6 is further disadvantageously reduced.
A second problem shown by the circular frame C in FIG. 50 is now described. As shown in FIGS. 50 or 55, portions of the major surface of the SOI layer 3 in proximity to the side walls 13 are selectively scraped off in the etching step for forming the side walls 13, whereby depressed portions 17 are defined in these portions. This phenomenon is caused by concentration of plasma, which is employed for the etching, in the vicinity of end portions of the FS insulating layer 4 including the side walls 13.
Each depressed portion 17 is so locally and heterogeneously defined that it is difficult to control a threshold voltage which is specific to the gate electrode 6 formed on an area including one depressed portion 17 at a prescribed level in excellent accuracy. Further, local thicknesses of the SOI layer 3 are reduced beyond a certain limit due to the depressed portions 17, and hence the body resistance of the SOI layer 3 is increased in portions of resistances R shown in FIG. 55. Thus, an effect of body fixing by the body contact electrodes may not be sufficiently attained.
Further, the surface of each side wall 13 is inwardly retreated due to the HF treatment performed before forming the gate insulating films 14, and hence a sharp step shown in the circular frame C in FIG. 50 is defined on the surface of the SOI layer 3. Consequently, a MOS transistor having a low threshold voltage is disadvantageously parasitically generated in the vicinity of this step. In addition, the gate electrode 6 which is formed on the surface of the SOI layer 3 is problematic in reliability, since the SOI layer 3 is exposed to the dry etching.
A third problem shown in the circular frame D in FIG. 50 is now described. FIGS. 56 to 58 are step diagrams showing fabrication steps causing this problem. As shown in FIG. 56, an oxidant infiltrates into areas shown in a grained manner in FIG. 56, i.e., the upper insulating layer 12, the side walls 13, and portions of the lower insulating layer 11 close to the edge portions 16 of the FS electrode 5, following oxidation for forming the gate insulating films 14 on the major surface of the SOI layer 3.
The infiltration depth E of the oxidant in the lower insulating layer 11 measured from each edge portion 16 is about 0.5 .mu.m in wet oxidation at 800.degree. C., which is a typical oxidation condition. Consequently, portions exposed to the oxidant are oxidized in the surfaces of the FS electrode 5 and the SOI layer 3.
FIG. 57 is an enlarged sectional view showing a portion around one edge portion 16. As shown by symbols F and G in FIG. 57, oxidation progresses also in the upper major surface of the SOI layer 3 and the lower major surface of the FS electrode 5 which are opposed to each other through the lower insulating layer 11 over the range from the edge portion 16 substantially to the infiltration depth E, due to the oxidant infiltrating into the lower insulating layer 11. In particular, the lower major surface of the FS electrode 5 is remarkably oxidized as shown by symbol G, since the FS electrode 5 is made of polysilicon containing an impurity in high concentration.
Consequently, the FS electrode 5 is so arcuately bent in the vicinity of the edge portion 16 as to upwardly direct the edge portion 16, as exaggeratedly shown in FIG. 57. Therefore, the distance between the FS electrode 5 and the gate electrode 6 is disadvantageously narrowed. This further aggravates the first problem. Namely, the electrostatic capacitance between the FS electrode 5 and the gate electrode 6 is so increased that the operating speed of the device 151 is reduced and the isolatability between these electrodes is reduced. Further, a short readily takes place across these electrodes.
In addition, the top portion 15 of each side wall 13 upwardly projects as shown in the circular frame H as a result of bending of the FS electrode 5, and hence the step of the side wall 13 is enlarged. This increases the plasma reflected to each side wall surface of the gate electrode 6 as shown by symbol a in the step of forming the gate electrode 6 by selective dry etching, as shown in FIG. 58. Consequently, the gate electrode 6 is disadvantageously partially narrowed. When the gate electrode 6 is partially narrowed, punch-through resistance is weakened.
In the conventional device 151, as hereinabove described, problems in the characteristics of the device such as the operating speed, reliability in the gate electrode 6 and the like remain unsolved, due to the structure of the FS insulating layer 4 for electrically insulating the FS electrode 5 and the gate electrode 6 from each other and the fabrication method.